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JESD204B Tx PCS IP Core
The JESD204B PCS IP Core enables both transmission and reception of data via a configurable number of Lanes to the SerDes interface, while guaranteeing data alignment and frame synchronization. The JESD204B PCS IP Core is responsible for frame generation, encoding, and scrambling for data transmission, as well as decoding, frame recovery, lane alignment and descrambling on data reception. The JESD204B PCS IP Core is fully compatible with the JEDEC JESD204B specification.
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Block Diagram of the JESD204B Tx PCS IP Core
JESD204B Tx IP
- JESD204B Tx-Rx PHY IP, Silicon Proven in TSMC 28HPC+
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- JESD204B Tx-Rx PHY IP, Silicon Proven in SMIC 14SF++
- JESD204B Tx-Rx PHY IP, Silicon Proven in UMC 28HPC
- JESD204B Tx-Rx PHY IP, Silicon Proven in UMC 55SP