The JESD204B PCS IP Core enables both transmission and reception of data via a configurable number of Lanes to the SerDes interface, while guaranteeing data alignment and frame synchronization. The JESD204B PCS IP Core is responsible for frame generation, encoding, and scrambling for data transmission, as well as decoding, frame recovery, lane alignment and descrambling on data reception. The JESD204B PCS IP Core is fully compatible with the JEDEC JESD204B specification.
- Fully compatible with the JESD204B.01, 2012 standard release.
- Includes the complete PCS functionality
- Flexible and highly configurable implementation
- Uses an AMBA APB4 interface for configuration setup and status reading purposes (I2C, SPI and custom interfaces are also available upon request)
- Supports a wide range of data converters over single and multiple serial lanes.
- Configurable number of converters per device (M), number of lanes (L) and converter resolution (N).
- High Density (HD) mode is available.
- Support of deterministic latency (in compliance with JESD204B.01 Subclass 1 and Subclass 2 requirements).
- Includes programmable debugging features
- Offers a variety of test patterns
- Generates a programmable interrupt signal
- Modular, completely synchronous design
- Complete, synthesizable RTL for the top-level design and all its sub-modules (VHDL or Verilog), all simulation, compilation and synthesis related scripts
- Fully comprehensive documentation (functional spec, integration spec, test plan, etc)
- Verification testbench and test suite
- Support during the IP core integration (coding and integration of IP core to the complete system, as well as verification and synthesis on system level)
- Wireless transceivers
- Signal processing cards
- Industrial, test and medical equipment
- Broadcast equipment
Block Diagram of the JESD204B Tx PCS IP Core