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JESD204B PCS Rx IP Core

The JESD204B RX Physical Coding Sublayer IP Core enables the reception of data via a configurable number of lanes from a Deserializer interface, while guaranteeing data alignment and frame synchronization. The JESD204B PCS Rx IP Core performs 8b/10b decoding, frame recovery, lane alignment, descrambling, and data demapping functions. In addition, it contains a set of test features, necessary to validate the data integrity on the serial interface. The HIP610 IP Core supports configurable number of DAC ports, each one having a width of up to 32 bits. The JESD204B PCS Rx IP Core offers the possibility to modify the behavior of the design based on the application requirements. This is done through the use of the design parameters, as well as via the Configuration Interface by programming the configuration registers.

特色

Fully compatible with the JESD204B.01, 2012 standard release
Uses an AMBA APB4 interface for configuration setup and status reading purposes (I2C, SPI and custom interfaces are also available upon request)
Supports a wide range of data converters over single and multiple serial lanes
Configurable number of converters per device (M), number of lanes (L) and converter resolution (N)
High Density (HD) mode is available
Provides initial lane alignment, frame alignment monitoring and correction, and character replacement
Support for multi-lane alignment
Support of deterministic latency (in compliance with JESD204B.01 Subclass 1 and Subclass 2 requirements)
Support for re-initialization via the data interface
Supports testing of Physical, Data Link and Transport layers
Generates a programmable interrupt signal
Modular, completely synchronous design

可交付内容

Complete, synthesizable RTL for the top-level design and all its sub-modules (VHDL or Verilog), all simulation, compilation and synthesis related scripts
Fully comprehensive documentation (functional spec, integration spec, test plan, etc)
Verification testbench and test suite
Support during the IP core integration (coding and integration of IP core to the complete system, as well as verification and synthesis on system level)