You are here:
JESD204B PCS Rx IP Core
The JESD204B RX Physical Coding Sublayer IP Core enables the reception of data via a configurable number of lanes from a Deserializer interface, while guaranteeing data alignment and frame synchronization. The JESD204B PCS Rx IP Core performs 8b/10b decoding, frame recovery, lane alignment, descrambling, and data demapping functions. In addition, it contains a set of test features, necessary to validate the data integrity on the serial interface. The HIP610 IP Core supports configurable number of DAC ports, each one having a width of up to 32 bits. The JESD204B PCS Rx IP Core offers the possibility to modify the behavior of the design based on the application requirements. This is done through the use of the design parameters, as well as via the Configuration Interface by programming the configuration registers.
查看 JESD204B PCS Rx IP Core 详细介绍：
- 查看 JESD204B PCS Rx IP Core 完整数据手册
- 联系 JESD204B PCS Rx IP Core 供应商
Block Diagram of the JESD204B PCS Rx IP Core
