You are here:
JESD204 PHY
The Xilinx® LogiCORE™ IP JESD204 PHY core implements a JESD204B physical interface to simplify sharing serial transceiver channels between transmit and receive cores. This core is not intended to be used standalone and should only be used only in conjunction with the JESD204 core.
Note: This core is provided as standalone IP for use in the JESD204 IP example design only.
Note: This core is provided as standalone IP for use in the JESD204 IP example design only.
查看 JESD204 PHY 详细介绍：
- 查看 JESD204 PHY 完整数据手册
- 联系 JESD204 PHY 供应商
Interface and Interconnect IP
- AXI- Interconnect : Advanced Extensible Interface Bus IP
- Universal Chiplet Interconnect Express (UCIe) Controller
- Serial Peripheral Interconnect Master & Slave Interface Controller
- UCIe/BoW BlueLynx™ Dual Mode PHY and subsystem IP for chiplet interconnect
- Physical Layer Interface Core
- PCIe 5.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC