MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, N7, N5A)
Java byte code processor
特色
- JavaTM Byte Code compatible
- only 20 Instructions need software assistance
- only two additional Instructions are neccesarry to write low level drivers
- Stack Cache (8-256 words) Stack handling is done by hardware
- 4 GB linear Address Space
- Memory mapped I/O
- 15 Interrupts in up to four Priority Levels
- Support for auto clear Interrupt
- Instruction and Data access can have variable timing
- programmable bus interface 8, 16 or 32 Bit
- Low Power Consumption
- ~25.000 gate equivalents
- 200 MHz @0.25µm
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