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IRIG-B Slave core
NetTimeLogic’s IRIG Slave Clock is a full hardware (FPGA) only implementation of a synchronization core able to synchronize to an IRIG-B004, B005, B006 and B007 Master. The whole encoding, conversion, algorithms and calculations are implemented in the core, no CPU is required. This allows running IRIG synchronization completely independent and standalone from the user application. The core can be configured either by signals or by an AXI4Light-Slave Register interface.
All calculations and corrections are implemented completely in HW.
All calculations and corrections are implemented completely in HW.
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Block Diagram of the IRIG-B Slave core
