MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, N7, N5A)
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IP Compiler for PCI Express x4 (Soft IP)
These popular PCIe MegaCore® functions (x1, x4, or x8 lane configurations) support all memory, I/O, configuration, and message transactions. The MegaCore functions have an optimized application interface to achieve maximum effective throughput. The MegaCore functions are also flexible and configurable, allowing customization for your specific needs. For example, the MegaCore functions support a configurable payload and a configurable retry buffer, and provide optional support for high-reliability features, such as ECRC and AER.
Altera has performed significant hardware testing of the PCIe x1, x4, and x8 endpoints to ensure a reliable solution. These MegaCore functions have been tested internally with a variety of x86 motherboards, PCIe switch chips, and embedded microprocessors. Additionally, the soft IP MegaCore functions were tested at the PCI-SIG compliance workshops and passed with high quality results, including a 100 percent passing rate for the PCI-SIG® gold tests.
Altera has performed significant hardware testing of the PCIe x1, x4, and x8 endpoints to ensure a reliable solution. These MegaCore functions have been tested internally with a variety of x86 motherboards, PCIe switch chips, and embedded microprocessors. Additionally, the soft IP MegaCore functions were tested at the PCI-SIG compliance workshops and passed with high quality results, including a 100 percent passing rate for the PCI-SIG® gold tests.
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