The EIP-76 TRNG is an advanced hardware based, technology independent True Random Number Generator. Security is now a basic requirement for all devices. To support that requirement, semiconductor designers must build strong cryptographic capabilities into their chips, capabilities that begin with a True Random Number Generator (TRNG). A TRNG is used for the generation of keys, initialization vectors, cookies, and nonces; it is an essential building block for all robust security solutions. Also, configurations are available to address safety standards for automotive applications. The TRNG-IP-76 True Random Number Generator provides semiconductor designers with an all-digital silicon-proven solution that has been thoroughly field tested and deployed in dozens of devices developed by the industry’s leading semiconductor companies.
- Patented test circuits on the oscillators to detect lockingto periodic signals.
- Repeating output data detection on NRBG and DRBG (compliant with [FIPS 140-2]).
- Hardware implemented ‘Repetition Count’ and ‘Adaptive Proportion’ tests on the Noise Source (compliant with [SP 800-90B]).
- Continuous tests on the Noise Source (compliant with [AIS-31]): ‘monobit test’, ‘poker test’, ‘runs test’, ‘longruns test’ and ‘Noise Source failure’.
- Secure random data buffer wipe-after-read and zeroize functions (compliant with [FIPS 140-2]).
- Secure reading mode where data is only available on request, for a (configurable) limited time.
- Automatic shutdown on fatal errors.
- Automatic de-tuning of FROs after lock detection.
- Various on-line and off-line integrity and known answer tests on the Conditioning Function, DRBG andself-test circuits.
- Configurations available with countermeasures against Fault Injection Attacks.
- True Random Number Generator
- Silicon-proven implementation
- Fast and easy to integrate into SoCs
- Flexible layered design
- Complete range of configurations
- World-class technical support
- Hardware Reference and Programmer Manual
- Integration Manual
- Noise & Entropy document
- Synthesizable Verilog RTL source code
- Self-checking RTL test bench, including test vectors and expected result vectors
- Simulation scripts
- Many different configurations possible:
- Conditioning Function support
- Fault Injection protected support
- (optional) Deterministic Random Bit Generator
- (optional) DMA handshake
- Gate count ranging from: 10.9k + 11.5k to 56k + 11.5k gates
- Up to 1 GHz
- For more information about this product or the all the different configurations, please contact Rambus: https://www.rambus.com/contact
- Key generation
- Random number generation
Block Diagram of the INSIDE Secure True Random Number Generator Engine