As part of INSIDE Secure’s award-winning silicon Intellectual Property (IP) product portfolio, the EIP-11 ARIA algorithm, as specified in RFC 5794. The accelerators include I/O registers, encryption and decryption cores, and the logic for feedback modes and key scheduling and GHASH. Besides the basic feedback modes such as CBC, CFB, OFB, and CTR, the EIP-11 also provides CCM, CMAC, GCM, XTS, f8 and f9.
Designed for fast integration, low gate count, and maximum performance, the ARIA Engine provide a reliable and cost-effective ARIA IP solution that is easy to integrate into SoC designs.
- Register interface.
- Key sizes: 128, 192 and 256 bits.
- Key scheduling hardware.
- Feedback modes: ECB, CBC, CFB, OFB, CTR.
- Protocol modes: CCM, CMAC, GCM and XCBC-MAC
- Optionally available: XTS, f8 and f9.
- Fully synchronous design
- High-speed ARIA solution.
- Silicon-proven implementation.
- Fast and easy to integrate into SoCs.
- Flexible layered design.
- Complete range of configurations.
- World-class technical support
- Hardware Reference and Programmer Manual
- Integration Manual
- Verification Specification
- Synthesizable Verilog RTL source code
- Self-checking RTL test bench, including test vectors and expected result vectors
- Simulation scripts
- 42.1K gates
- GCM: 5.12 bits/clk CCM: 2.56 bits/clk Other: 5.33 bits/clk
- up to 640 MHz