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INNOLINK Chiplet PHY&Controller
Innosilicon INNOLINK™ IP provides a leading-edge chiplet solution allowing massive amounts of low-latency data to pass seamlessly between smaller chips as if they were all on the same bus. Chiplets, defined as independent functional blocks making up a large chip, are pivotal in this new era of heterogeneous integration to achieve performance and efficiency gains. Based on this, Innosilicon launches the INNOLINK™ chiplet solution as a critical enabler of the power- and cost-efficient die-to-die (D2D), chip-to-chip (C2C), board-to-board (B2B) and package-to-package (P2P) connectivity for data center, networking, 5G, HPC and AI applications.
Innosilicon INNOLINK™ IP is designed to maximize bandwidth between dies / chips / boards / packages, compared to other interfaces available today, at lower power and smaller area budgets. By offering three interconnect options (A/B/C), INNOLINK™ IP can be tailored to customer’s different requirements with an easy-to-use system interface. It is architected for high programmability and flexibility, Maximum bandwidth efficiency up to 3.4Tbps while maintaining signal integrity and low latency. Adopting the INNOLINK™ IP in your system will definitely benefit high performance computing ASICs/FPGAs, such as CPU, GPU, AI accelerator, and much more.
Innosilicon INNOLINK™ IP is designed to maximize bandwidth between dies / chips / boards / packages, compared to other interfaces available today, at lower power and smaller area budgets. By offering three interconnect options (A/B/C), INNOLINK™ IP can be tailored to customer’s different requirements with an easy-to-use system interface. It is architected for high programmability and flexibility, Maximum bandwidth efficiency up to 3.4Tbps while maintaining signal integrity and low latency. Adopting the INNOLINK™ IP in your system will definitely benefit high performance computing ASICs/FPGAs, such as CPU, GPU, AI accelerator, and much more.
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