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INNOLINK-B PHY
Innosilicon can provide different Die2Die solution for customer depend on package type, Following is Innosilicon Die2Die IP family:
Innolink-A, Serdes base, up to 32/56Gbps/pair, long reach, chip to chip or board to board connection.
Innolink-B, gddr like, single ended, up to 24Gbps/pin, typical MCM or short PCB application, bump pitch 100um~180um.
Innolink-C, gddr and lpddr5 like, optimized for silicon interposer, super small IO and 0.4V IO voltage, max 24Gbps/pin, bump pitch 40um~100um.
This document contains specifications of INNOLINK-B, Innosilicon can provide only PHY solution, and we can also provide PHY + Controller solution, this data sheet is for PHY solution with DFI like interface. Innolink PHY is full harden IP, Innolink Controller is soft IP.
INNOLINK-B is designed to perform high speed data communication between dies or chips. The physical implementation methodology of INNOLINK-B is a DDR-like interface, which use single ended signal for IO interface, forward clock is used for Rx data sampling.
In this document, the DDR-like INNOLINK-B is adopted, Innolink-B use 16bit Tx DQs +16bit Rx DQs per module , when each DQ runs at 24Gbps and configured with two modules (32bit Tx + 32bit Rx), total bandwidth will be 768Gbps for TX and 768Gbps for RX. Innolink-B can be configured to 1/2/4/8/16/32 modules, and this data sheet is an example of 1 module.
Innolink can be easily integrated with innolink controller, and IO input/output direction can be software defined.
Innolink-A, Serdes base, up to 32/56Gbps/pair, long reach, chip to chip or board to board connection.
Innolink-B, gddr like, single ended, up to 24Gbps/pin, typical MCM or short PCB application, bump pitch 100um~180um.
Innolink-C, gddr and lpddr5 like, optimized for silicon interposer, super small IO and 0.4V IO voltage, max 24Gbps/pin, bump pitch 40um~100um.
This document contains specifications of INNOLINK-B, Innosilicon can provide only PHY solution, and we can also provide PHY + Controller solution, this data sheet is for PHY solution with DFI like interface. Innolink PHY is full harden IP, Innolink Controller is soft IP.
INNOLINK-B is designed to perform high speed data communication between dies or chips. The physical implementation methodology of INNOLINK-B is a DDR-like interface, which use single ended signal for IO interface, forward clock is used for Rx data sampling.
In this document, the DDR-like INNOLINK-B is adopted, Innolink-B use 16bit Tx DQs +16bit Rx DQs per module , when each DQ runs at 24Gbps and configured with two modules (32bit Tx + 32bit Rx), total bandwidth will be 768Gbps for TX and 768Gbps for RX. Innolink-B can be configured to 1/2/4/8/16/32 modules, and this data sheet is an example of 1 module.
Innolink can be easily integrated with innolink controller, and IO input/output direction can be software defined.
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