IEEE 754 Floating Point Coprocessor

The A2F3 is a fully synthesizable module implemented in Verilog RTL. It is a co-processor unit providing floating-point computation compliant with the ANSI/IEEE Std 754-1985, IEEE Standard for Binary Floating-Point Arithmetic (IEEE Standard). It is designed to provide high performance floating-point computation while minimizing die size and power. Pipelined, single-cycle throughput operation is available for all operations except for divide, remainder and square-root.

Full IEEE compliance is supported with a dynamic pipelining technique that enables the A2F3 to support clock rates of multiple Giga-Hertz, foundry dependant (of course), with only a 4-stage pipeline. Further the A2FP can now be easily configured to support multiple independent pipelines each with its own selection of floating-point operations. This allows support for multiple instruction issue per cycle as well as chaining to support parallel and vector operations.

The A2F3 is supplied either as an execution unit to support integration into embedded processors or combined with the A2P to create a co-processor that provides standalone engines that can be tightly or loosely coupled to other processors in a system. Typical applications include XML processing, FFT engines, high-performance GPS as well as general purpose scientific number crunching.

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