IBM 65nm LVDS Transmitter

The LVDS transmitter converts 28-bit data into 4-pair LVDS data stream. A phase-locked transmit clock is transmitted in parallel with the data stream over the fifth LVDS channel. Every transmission cycle 28 bits of input data are sampled and transmitted. The transmitter can be programmed for either Rising-edge strobe or Falling-edge strobe through a dedicated pin. The transmitter supports Spread Spectrum Clocking type of signal input and can accurately track Spread Spectrum Clock/Data input.

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