I2S Receiver/Transmitter

The logiI2S IP core from Xylon's logicBRICKS™IP library is a module for I2S audio data receiving and/or transmitting. The logiI2S IP's RX and TX submodules are I2S masters only.

The logiI2S is, like the other IP cores from Xylon logicBRICKS™ IP library, fully embedded into Xilinx Platform Studio (XPS) and the EDK.

Therefore it can be easily customized and tuned for optimal slice consumption and features set.

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