MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, N7, N5A)
You are here:
I2S Controller IP Core- Two Channel
The Arasan I2S Controller IP Core is a two-channel I2S serial audio controller compliant to the Philips* Inter-IC Sound specification. The I2S bus is used for connecting audio components such as speakers, DACs, or audio subsystems. The Arasan I2S Controller IP Core provides a 32-bit parallel processor bus as the application interface.
The controller’s I2S interface consists of one transmitter and one receiver. Each channel can be programmed as an I2S master or an I2S slave. The Bit Clock (BLCK) and Left and Right Clock (LRCK) provide synchronization for the transmit and receive data. The I2S Controller IP supports 44.1KHz audio sampling rates. DAC/ADC resolution is configurable from 8-bit to 32-bit.
The controller’s I2S interface consists of one transmitter and one receiver. Each channel can be programmed as an I2S master or an I2S slave. The Bit Clock (BLCK) and Left and Right Clock (LRCK) provide synchronization for the transmit and receive data. The I2S Controller IP supports 44.1KHz audio sampling rates. DAC/ADC resolution is configurable from 8-bit to 32-bit.
查看 I2S Controller IP Core- Two Channel 详细介绍：
- 查看 I2S Controller IP Core- Two Channel 完整数据手册
- 联系 I2S Controller IP Core- Two Channel 供应商
I2S Controller IP
- APB Fundamental Peripheral IP, Serial Interface controller for multiple frame formats, SSP (by TI), SPI (by Motorola), Microwire (by NS), I2S (by Philips), AC - link (by Intel) and SPDIF (by Intel), Soft IP
- Dolphin I2S Controller & PHY
- I2S Controller IP
- HDMI 2.0 Tx PHY & Controller IP, Silicon Proven in TSMC 12FFC
- I2S/TDM Multichannel Audio Transceiver
- MIPI SLIMbus Host Controller v2.0