Adaptive Clock Generation Module for DVFS and Droop Response
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I2C/SMBus Master/Slave Controller w/FIFO (AXI/AHB/APB)
The Digital Blocks DB-I2C-SMBus-MS-AMBA Controller IP Core is an I2C/SMBus Master/Slave Controller, interfacing a microprocessor via the AMBA AXI, AHB, or APB Bus to an SMBus Interconnect. Both I2C and SMBus protocols are supported.
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Block Diagram of the I2C/SMBus Master/Slave Controller w/FIFO (AXI/AHB/APB)
