You are here:
I2C/SMBus Master/Slave Controller w/FIFO (AXI/AHB/APB)
The Digital Blocks DB-I2C-SMBus-MS-AMBA Controller IP Core is an I2C/SMBus Master/Slave Controller, interfacing a microprocessor via the AMBA AXI, AHB, or APB Bus to an SMBus Interconnect. Both I2C and SMBus protocols are supported.
查看 I2C/SMBus Master/Slave Controller w/FIFO (AXI/AHB/APB) 详细介绍：
- 查看 I2C/SMBus Master/Slave Controller w/FIFO (AXI/AHB/APB) 完整数据手册
- 联系 I2C/SMBus Master/Slave Controller w/FIFO (AXI/AHB/APB) 供应商
Block Diagram of the I2C/SMBus Master/Slave Controller w/FIFO (AXI/AHB/APB)
