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I2C Slave with APB Master Bridge (I2C2APB)
The DB-I2C-S-APB-BRIDGE is an I2C Slave Controller IP Core focused on low VLSI footprint ASIC / ASSP designs not requiring internal configuration & control registers (and thus no local host CPU required). The DB-I2C-S-APB-BRIDGE processes the I2C protocol & physical layers, and receives & transmits bytes with respect to the I2C payload via a bridge APB Master Interface to user registers or memory.
The DB-I2C-S-APB-BRIDGE runs off the APB Master external clock input within the ASIC / ASSP, providing a synchronous design while offering I2C spike filtering of SDA and SCL.
The DB-I2C-S-APB-BRIDGE runs off the APB Master external clock input within the ASIC / ASSP, providing a synchronous design while offering I2C spike filtering of SDA and SCL.
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I2C Slave Controller IP
- I2C and SPI Master/Slave Controller
- I2C Master/Slave Controller Core IP
- I2C Master / Slave Controller w/FIFO (AHB & AHB-Lite Bus)
- I2C Master / Slave Controller w/FIFO (APB Bus)
- Hs-Mode I2C Controller - 3.4 Mbps, Master / Slave w/FIFO
- I2C Slave Controller - Low Power, Low Noise Config of User Registers