Display LVDS/MIPI D-PHY/sub-LVDS combo Transmitter 1.0G/2.5G/1.0Gbps 10-Lane
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I2C Slave
The I²C slave IP is fully synthesizable core and compatible with Phillips I²C standard. The IP uses I²C Bus Protocol which helps maximize the hardware efficiency and minimize the interfaces.
The I²C Slave IP Core is provided as Altera SOPC Builder ready component and integrates easily into any SOPC Builder generated system.
The I²C Slave IP Core is provided as Altera SOPC Builder ready component and integrates easily into any SOPC Builder generated system.
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