You are here:
I2C Slave Controller w/FIFO (APB Bus)
The Digital Blocks DB-I2C-S-APB Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC or other high performance microprocessor via the AMBA 2.0 APB System Interconnect Fabric to an I2C Bus. The I2C is a two-wire bidirectional interface standard (SCL is Clock, SDA is Data) for transfer of bytes of information between two or more compliant I2C devices.
The DB-I2C-S-APB is a Slave I2C Controller that controls the Transmit or Receive of data to or from external Master I2C devices. Figure 1 depicts the system view of the DB-I2C-S-APB Controller IP Core embedded within an integrated circuit device.
The DB-I2C-S-APB is a Slave I2C Controller that controls the Transmit or Receive of data to or from external Master I2C devices. Figure 1 depicts the system view of the DB-I2C-S-APB Controller IP Core embedded within an integrated circuit device.
查看 I2C Slave Controller w/FIFO (APB Bus) 详细介绍:
- 查看 I2C Slave Controller w/FIFO (APB Bus) 完整数据手册
- 联系 I2C Slave Controller w/FIFO (APB Bus) 供应商