MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, N7, N5A)
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I2C Master-Slave-PIO IP Core
The I2C Master/Slave/PIO IP Core is a complete I2C solution offering three modes of operation and support for standard I2C bus transmission speeds. The I2C Master/Slave core provide a generic memory-mapped bus interface. Also designed as an Altera SOPC Builder Ready component, it integrates easily into any SOPC Builder generated system using an Nios® II Avalon bus.
The I2C PIO Slave core is provided as an Altera Quartus II Megafunction and integrated into the Altera MegaWizard Plug-in Manager.
The core is optimized for all Altera FPGA's, including the newest generation of Stratix, Arria, Cyclone and MAX II devices.
Sample applications for uClinux and HAL are provided for components on the I2C bus.
The I2C PIO Slave core is provided as an Altera Quartus II Megafunction and integrated into the Altera MegaWizard Plug-in Manager.
The core is optimized for all Altera FPGA's, including the newest generation of Stratix, Arria, Cyclone and MAX II devices.
Sample applications for uClinux and HAL are provided for components on the I2C bus.
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Block Diagram of the I2C Master-Slave-PIO IP Core
