MIPI D-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
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I2C Master/Slave Interface
CoreI2C provides an APB-driven serial interface, supporting I2C, SMBus, and PMBus data transfers. Several Verilog/VHDL parameters are available to minimize FPGA fabric area for a given application. CoreI2C also allows for multiple I2C channels, reusing logic across channels to reduce overall tile count.
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I2C Master/Slave Interface IP
- I2C Master / Slave Controller w/FIFO (AHB & AHB-Lite Bus)
- I2C Master / Slave Controller w/FIFO (APB Bus)
- I2C Master / Slave Controller w/FIFO (AXI & AXI-Lite Bus)
- I2C Bus Master / Slave Controller Interface with FIFO
- A bridge to convert the slave SPI interface to the master I2C interface and vice versa
- I2C Bus Interface - Master/Slave