I2C Master Controller w/FIFO (AHB & AHB-Lite Bus)

The Digital Blocks DB-I2C-M-AHB Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC, or other high performance microprocessor via the AMBA 2.0 APB System Interconnect Fabric to an I2C Bus. The I2C is a two-wire bidirectional interface standard (SCL is Clock, SDA is Data) for transfer of bytes of information between two or more compliant I2C devices, typically with a microprocessor behind the master controller and one or more master / slave or slave devices.

Digital Blocks offers I2C Controller Master/Slave, Master only, and Slave only IP with AXI / AHB / APB / Avalon / Qsys Interfaces. In addition, besides interfacing to a CPU, the I2C Controllers can transfer blocks of data directly between System Memory or Registers and the I2C Bus.

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