Entry-level APU/embedded core with Linux and SMP configurations support
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I2C Bus Interface - Master
The I2C is a two-wire, bi-directional serial bus, that provides a simple and efficient method of short distance data transmission between many devices. The DI2CM core provides an interface between a microprocessor/microcontroller and the I2C bus. It can work as a master transmitter or a master receiver - depending on a working mode, determined by the microprocessor/microcontroller. The DI2CM core incorporates all features required by the latest I2C specification, including clock synchronization, arbitration, multi-master systems and high-speed transmission mode. Built-in timer allows operation from a wide range of the clk frequencies.
The DI2CM is a technology independent design, that can be implemented in a variety of process technologies.
The DI2CM is a technology independent design, that can be implemented in a variety of process technologies.
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I2C IP
- I2C Host / Device Bus Controller
- DO-254 I2C Master Serial Interface Controller 1.00a
- A 28nm Wirebond IO library with dynamically switchable 1.8V/ 3.3V GPIO, 5V I2C open-drain, 1.8V & 3.3V analog, OTP program cell, and HDMI & LVDS protection macros - featured across a variety of metal stack and pad configuration options
- A 22nm Wirebond IO library with dynamically switchable 1.8V/3.3V GPIO, 3.3V I2C open-drain, & analog cells
- A 65nm Wirebond IO library with 1-3.3V GPIO, 3.3V pulse-width modulation cell, I2C & SVID open-drain, 3.3V & 5V analog and OTP program cell
- Open-drain I2C and SMBUS, DDC, CEC & HPD IO offerings in TSMC Technologies