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I2C Bus Interface
The serial controller interface (Single Master) core uses a two-wire bus for communicating between integrated circuits or standard peripherals like smart LCDs and keypads. The core contains the entire physical and data link layers, allowing it to handle bus timing and
frame generation/extraction, and thus reducing overhead from the system application. A flexible parallel interface is used for on-chip data transfer, facilitating integration of the iniSCI core to the rest of the system.
frame generation/extraction, and thus reducing overhead from the system application. A flexible parallel interface is used for on-chip data transfer, facilitating integration of the iniSCI core to the rest of the system.
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Block Diagram of the I2C Bus Interface

I2C IP
- DO-254 I2C Master Serial Interface Controller 1.00a
- TSMC based IO & ESD solutions supporting GPIO, I2C,RGMII, SD, LVDS, HDMI & analog/RF across multiple technology nodes
- A 28nm Wirebond IO library with dynamically switchable 1.8V/ 3.3V GPIO, 5V I2C open-drain, 1.8V & 3.3V analog, OTP program cell, and HDMI & LVDS protection macros - featured across a variety of metal stack and pad configuration options
- A 16nm/12nm Flip-Chip IO library with dynamically switchable 1.8V/3.3V GPIO, 5V I2C open-drain, 5V OTP and 1.8V / 3.3V analog
- A 65nm Wirebond IO library with 1-3.3V GPIO, 3.3V pulse-width modulation cell, I2C & SVID open-drain, 3.3V & 5V analog and OTP program cell
- Open-drain I2C and SMBUS, DDC, CEC & HPD IO offerings in TSMC Technologies