180nm FTP Non Volatile Memory for Standard CMOS Logic Process
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Hs-Mode I2C Controller - 3.4 Mbps, Slave w/FIFO
The Hs-Mode I2C Controller IP Core interfaces user Registers to an I2C Bus or Memory (SDRAM / SRAM / Flash / FIFO) or any Peripheral or CPU connecting through an internal AHB / APB / AXI / Avalon / Qsys Bus to an I2C Bus in Hs-Mode (3.4 Mbit/s) / Fast-Mode Plus (1 Mbit/s) / Fast-Mode (400 Kbit/s) / Standard-Mode (100 Kbit/s).
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Block Diagram of the Hs-Mode I2C Controller - 3.4 Mbps, Slave w/FIFO
