180nm FTP Non Volatile Memory for Standard CMOS Logic Process
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Hs-Mode I2C Controller - 3.4 Mbps, Master w/FIFO
The Hs-Mode I2C Controller IP Core interfaces a microprocessor via the AMBA AXI / AHB / APB Bus or Avalon / Qsys Bus to an I2C Bus in Hs-Mode (3.4 Mbit/s) / Fast-Mode Plus (1 Mbit/s) / Fast-Mode (400 Kbit/s) / Standard-Mode (100 Kbit/s). The Hs-Mode I2C Controller IP Core can also interface Memory (e.g. SDRAM / SRAM / FLASH) to an I2C Bus
The I2C is a two-wire bidirectional interface standard (SCL is Clock, SDA is Data) for transfer of bytes of information between two or more compliant I2C devices, typically with a microprocessor behind the master / slave controller and one or more master / slave devices.
The I2C is a two-wire bidirectional interface standard (SCL is Clock, SDA is Data) for transfer of bytes of information between two or more compliant I2C devices, typically with a microprocessor behind the master / slave controller and one or more master / slave devices.
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Block Diagram of the Hs-Mode I2C Controller - 3.4 Mbps, Master w/FIFO
