This is a Reed Solomon decoder capable of operating with shortened codewords. The basic mother rate is (N,K) = (255,239) which has 16 parity bytes and can correct up to 8 corrupted bytes (up to 8 bits in a byte can be in error). The mother rate can be shortened to N_MAX <= 255 but still retains the ability to correct up to 8 bytes in error. The decoder only outputs K bytes per N bytes in, and these are in natural order. It has enough memory to operate continuously with one byte per clock cycle on its input, leading to a net rate of 8*CLK bps of coded data. The codeword length is programmable at run-time.
- Based on industry standard generating polynomials
- Supports shortening
- Supports erasures
- Run-time programmable codeword length
- High throughput
- Low FPGA memory usage compared to competitors
- Low FPGA logic usage