MIPI C-PHY v1.2 D-PHY v2.1 RX 2 trios/2 Lanes in TSMC (16nm,N6, N5)
High speed universal LVDS Transceiver
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Block Diagram of the High speed universal LVDS Transceiver

LVDS IP
- TSMC GF LVDS Tx/Rx with optional CMOS I/O
- TSMC FPD-Link / OpenLDI / LVDS forwarded clock SERDES Link
- TSMC 3nm (N3E) 1.5V LVDS
- TSMC 3nm (N3E) 1.2V LVDS Tx/Rx with 1.8V BGR
- Display LVDS/MIPI D-PHY/sub-LVDS combo Transmitter 1.0G/2.5G/1.0Gbps 10-Lane
- LVDS IO handling data rate up to 50Mbps with maximum loading 60pF