TC3404 is a 2D TPC decoder that is optimised for high-speed. A single Core achieves in excess of 200 Mbps user rate with the latest FPGA families (Stratix2, Virtex4). For cost-sensitive application requiring less bitrate, refer to our TC3401 product. For applications reguiring high code gain, refer to our TC30xx family.
- Best use of FPGA for very high bitrate (up to 230 Mbps user bitrate at 4 iterations).
- Supports all modes of IEEE-802.16a TPCs
- Supports large block sizes (up to 65Kbits).
- Highly programmable
- On-the-fly change of code
- Reduced latency (bank-swapping option)
- Dedicated or micro-controller interface
- TC3404 is ideal for applications requiring high-speed (~200 Mbps uer rate) from a single Core.
- Synthesized FPGA netlist for Altera's or Xilinx's
- Behavioral C-model library
- RTL-model library for Modelsim
- SW executable for test vector generation
- Test bench VHDL source code