High speed/throughput, low power, Viterbi compiler - (including WiMAX, UWB, 802.11n, 3GPP LTE, 802.16m)

特色

• K=7 (64 states), Parameterizable polynomials.
• Decoder's basic rate, 1/2 or 1/3 or 1/4 or 1/5. Other rates can be supplied by external puncturing.
• Decoding of 1 or 2 or 3 bits per clock algorithms.
• Parameterizable input soft width.
• Parameterizable traceback length (memory depth).
• On the fly configurable traceback length, to support low latency.
• Zero delay between packets.
• Memory type (SRAM / register file), supports Altera/Xilinx coding style for easy synthesis.
• Optional controls (decoder_en - for discontinuous data stream, decoder_abort - to reset the decoder).
• Supports low power features (clock gating, grey decoding, ...)
• The compiler generates Viterbi decoder + test bench + behavioral model.
• All-synchronous design using a single clock, except for global asynchronous reset.
• The decoder supports the following features:
• Supports ALL 802.X standards and data rates.
• Supports all termination methods: zero tail bits (802.11), tail-biting (WiMAX), partial zero tail bits (UWB)
• On the fly configurable convergence length (to support low latency where needed).
• Fits both ASIC and FPGA.

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