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High Speed SelectIO Wizard
The LogiCORE™ IP UltraScale™ High Speed SelectIO Wizard generates customized HDL wrappers to configures the UltraScale FPGA on-chip SelectIO. The wizard’s customization GUI allows users to configure one bank with up to two interfaces of high-speed Select IO Interfaces using the Native mode components. The GUI will set up the Native mode components clocking and capture, primites. The capture methods and IO standards may be selected as well as pin planning.
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Interface and Interconnect IP
- AXI- Interconnect : Advanced Extensible Interface Bus IP
- Universal Chiplet Interconnect Express (UCIe) Controller
- Serial Peripheral Interconnect Master & Slave Interface Controller
- UCIe/BoW BlueLynx™ Dual Mode PHY and subsystem IP for chiplet interconnect
- Physical Layer Interface Core
- PCIe 5.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC