High Speed PLL CML to Complementary - TSMC CLN3P
The PLL macro is implemented in Analog Bits’ proprietary architecture that uses core and 1.2V IO devices. In order to minimize noise coupling and maximize ease of use, the PLL incorporates a proprietary ESD structure, which is proven in several generations of processes. Eliminating band-gaps and integrating all on-chip components such as capacitors and ESD structures, helps the jitter performance significantly and reduces stand-by power.
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