high-speed interface for high-performance DDR3 PHY
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Block Diagram of the high-speed interface for high-performance DDR3 PHY
DDR3 PHY IP
- DDR3 PHY - GLOBALFOUNDRIES 12nm
- DDR3/4 and LPDDR2/3/4/4x Combo PHY&MAC
- DDR3/DDR4 IP solution with high performance and low power
- Command/Address Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for Solder bump Flip chip version ; UMC 40nm LP LowK Logic Process
- DDR3/LPDDR23 PHY - 55LL
- DDR3/LPDDR23 PHY - 65LL