Original Lossless codec IP core - Full HD 30fps@126MHz (1Sample/clk)
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high-speed interface for high-performance DDR3 PHY
The T40LP_DDR3TOPV01 IP is a high-speed interface for high-performance DDR3 PHY applications. This IP based on TSMC 40nm LP process. The operation speed is up to 800MHz (1600Mbps) at 1.5V voltage for DDR3 application. The on-die termination (ODT) is provided to improve the signal integrity (SI).
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Block Diagram of the high-speed interface for high-performance DDR3 PHY
