NVM Anti-Fuse OTP NeoFuse in UMC (110nm, 80nm, 55nm, 40nm, 28nm, 22nm)
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High Performance NVMe for PCIe-based storage
Typical storage controllers are composed of a communication interface and a Nandflash controller. In this case, all the data flow is managed by the external host processor. However, this architecture cannot sustain high performance applications. The IPM-NVMe_Device IP core designed by IP-Maker is a powerful data transfer manager integrated into the PCIe SSD Controller between the communication interface and the Nandflash controller, therefore off-loading the host CPU.
The IP-Maker NVMe IP is UNH-IOL NVM Express compliant. It is part of the official NVMe integrator’s list: https://www.iol.unh.edu/registry/nvme
The IP-Maker NVMe IP is UNH-IOL NVM Express compliant. It is part of the official NVMe integrator’s list: https://www.iol.unh.edu/registry/nvme
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Block Diagram of the High Performance NVMe for PCIe-based storage
Video Demo of the High Performance NVMe for PCIe-based storage
This is the NVM Express demo from IP-Maker demonstrated at Flash Memory Summit 2012, Santa Clara, CA. The NVMe IP is integrated in a FPGA-based board including all the mandatory features of the NVM Express specification 1.0d. NVMe protocol is observed with a protocol analyzer from Teledyne Lecroy.