PACT offers XPP-III cores as synthesizable Verilog RTL Code. XPP-III is built from only a few different components which are linked with pipelined point-to point connections. This allows to arrange and link all IP components (Such as the Array, the FNC-PAEs, Arbiter and DMA Controller) to the required top-level design. Similarily, the size of the array can be scaled easily. The components can be synthesized and routed separately wich may simplify the floorplanning and backend process.
- The XPP-III IP comprises all modules which are required for the processing kernel of a SoC. External RAM controllers and default peripherals (PCI-e, USB etc.) can simply be connected to the kernel's I/O interfaces. The XPP-III core requires a single clock.
- Word size: 16-bit
- parameterisable number of horizontal data and event channels
- RAM-PAE size 512 words
- The Function PAE includes local RAM (TCM) and L1 I-cache
- 4D address generators for XPP-array ports
- DMA controllers for data transfer and array reconfiguration
- Interrupt controller
- Function PAE Memory arbiter and L2 cache controller
- Boot controller
- Function PAE 16-bit peripherals Bus
- The IP comes with a comprehensive test suite with almost 100% test coverage. All connections and global signals are fed hierarchically through the PAEs. The layout of a PAE-macro must allow for the arrangement in a rectangular array - this means the macros are abutting e.g. similar to a RAM array. Therefore, for back-end processing one can use a generator approach to create the top level of a specific XPP-III. The blocks integrate scan paths for almost 100% test-coverage and debugging-support through JTAG.
- Implementations of the RTL code have proven that even large arrays can be synthesized, routed and verified in a reasonable time. The RTL code is co-developed with the System-C processor model, thus simulation and the hardware show the identical cycle accurate behaviour.