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High Performance, Low Latency PCIe Gen5 PHY
Terminus Circuits offers best-in-class PHY IP for PCI Express Gen 5/4/3/2/1. The PHY is designed for low latency, low power, small form factor, high interface speeds intended for high performance computing. It is designed with a system-oriented approach to maximize flexibility and ease of integration for our customers.
The PMA ( Physical Media Attachment) is delivered as hard macro and the PCS ( Physical Coding sublayer ) as a synthesizable soft macro. The integrated PHY ( PCS+PMA) of PCIe Gen 5 is backward compatible to PCIe Gen 4/3/2/1/ and designed for various applications like chip_to_chip communication, SSD, HPC for enterprise solutions supporting upto 36dB channel loss. Our PHY architecture support wide range of links with our unique CMU (Clock Management Unit).
PHY IP provides high-performance low power architecture having multi-lane capability for the high-bandwidth applications. It meets the needs of today’s high speed chip-to-chip, board-to-board, and backplane interfaces while being low in power and area.
The PMA ( Physical Media Attachment) is delivered as hard macro and the PCS ( Physical Coding sublayer ) as a synthesizable soft macro. The integrated PHY ( PCS+PMA) of PCIe Gen 5 is backward compatible to PCIe Gen 4/3/2/1/ and designed for various applications like chip_to_chip communication, SSD, HPC for enterprise solutions supporting upto 36dB channel loss. Our PHY architecture support wide range of links with our unique CMU (Clock Management Unit).
PHY IP provides high-performance low power architecture having multi-lane capability for the high-bandwidth applications. It meets the needs of today’s high speed chip-to-chip, board-to-board, and backplane interfaces while being low in power and area.
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Block Diagram of the High Performance, Low Latency PCIe Gen5 PHY
