High Performance, Low Latency PCIe Gen5 PHY
The PMA ( Physical Media Attachment) is delivered as hard macro and the PCS ( Physical Coding sublayer ) as a synthesizable soft macro. The integrated PHY ( PCS+PMA) of PCIe Gen 5 is backward compatible to PCIe Gen 4/3/2/1/ and designed for various applications like chip_to_chip communication, SSD, HPC for enterprise solutions supporting upto 36dB channel loss. Our PHY architecture support wide range of links with our unique CMU (Clock Management Unit).
PHY IP provides high-performance low power architecture having multi-lane capability for the high-bandwidth applications. It meets the needs of today’s high speed chip-to-chip, board-to-board, and backplane interfaces while being low in power and area.
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Block Diagram of the High Performance, Low Latency PCIe Gen5 PHY

PCIe 5.0 PHY IP
- PCIe 5.0 SerDes PHY
- PCIe 5.0 PHY in TSMC (16nm)
- PHY/PCS Logical Sub-Block IP Core for PCIe supporting PCIe 5.0, 4.0, 3.1 PHY/PMA and compliant to the PIPE 5.2 and 4.4.1 Specifications
- PCIe 4.0 PHY IP with 16GT/s optimized for low power consumption (Silicon Proven in TSMC 28HPC+)
- PCIe 5.0 Customizable Embedded Multi-port Switch
- PCIe 5.0 Controller supporting Endpoint, Root Port, Switch, Bridge and advanced features