高性能，具有高代码密度的CPU，可用以实现复杂的控制。

特色

• High Throughput RISC Core
• Excellent Code Density
• 2.28 DMIPS/MHz
• 5-stage pipeline
• High Clock Frequency (> 400MHz in 90nm)
• Optional Instruction Cache
• Optional Data Cache
• Optional co-processors (user & Cortus designed)
• Integer Divider
• Integer Multiply
• Up to 250 Low Latency Vectored Interrupts
• Dual & Multi-core Capable

优势

• High performance CPU
• Compact silicon footprint, less silicon area
• High maximum clock frequency, more time sleeping
• Good Code Density, less Flash memory required
• Dual and Multi-Core, more performance without exploding consumption
• Co-processor interface, add algorithmic functionality in hardware, save time and power.
• Caches, more complex memory architectures are possible
• RTOS support: FreeRTOS, uCLinux, uC/OS II, uC/OSIII, TargetOS
• Full Development Environment
• Optional Ethernet 10/100 MAC and USB2.0 Peripheral
• Optional JTAG-Ethernet Debug Solution

可交付内容

• Full Verilog Source Code
• Full Toolchain
• Graphical Development Environment
• Debugger
• Standard Peripherals
• Full Documentation
• Complete Integration Guide

应用

• Powerline communications
• Vision systems (e.g. surveillance, automotive)
• High performance embedded systems
• Symmetric multi-processing systems

Block Diagram of the 高性能，具有高代码密度的CPU，可用以实现复杂的控制。

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