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High performance dual-issue, out-of-order, 7-stage pipeline superscalar core
RiVAI-R1 is a dual-issue, Out-of-Order execution, 7-stage pipeline, 32-bit RISC-V CPU core IP that supports the RV32IMFAC instruction sets, as well as partial P extension. It is a real-time high-performance CPU IP, which can boost the performance of voice, audio, video, image and AI processing. Its “F” extensions support IEEE 754-compliant single precision floating point instructions, as well. Including register renaming, the memory access width is 256 bits. This greatly enhances memory bandwidth and reduces memory latencies for applications with intensive memory accesses. In addition, RiVAI-R1 features an advanced low-power, dynamic branch-prediction mechanism for efficient branch execution, instruction and data caches, local memories, and ECC error protection. It also includes a vectored and preemptive interrupt controller to serve diversified system events, an AHB bus, rich power management, and JTAG debug and trace interface for software development support.
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Block Diagram of the High performance dual-issue, out-of-order, 7-stage pipeline superscalar core
