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High Density Via Programmable ROM Compiler - TSMC 28 nm CLN28LE

ARM offers an array of silicon proven SRAM, Register File and ROM memory compilers for all types of SoC designs ranging from performance critical to cost sensitive and low power applications. As part of the ARM Processor / Graphics Optimized packages, ARM Fast Cache Instances deliver tuned performance, power and area when building ARM Processors, Graphics and System IP.

特色

High density and low power architecture
Multiple power management modes with power gating and multi-voltage operation
Flexible margining features
Optional integrated pipeline
Soft Error repair
Advanced test features
Pseudo Scan

优势

Minimizes die area to reduce die and packaging cost
Flexible power management allows packaging cost reduction, competitive product with higher battery life
Allows yield/performance tradeoff
Allows high throughput
Enables yield optimization
Enhances product quality and minimizes field returns
Cuts down test time drastically by orders of magnitude reducing overall product test cost significantly
Improved product quality lowers field failures

可交付内容

Front End (FE) and Back End (FB) views with full suite of design views and models that support most of the industry's popular design tools can be downloaded from the ARM DesignStart web site at: http://www.arm.com/support/designstart.php