The High Data Rate Modulator IP Core efficiently realizes the digital baseband section of a high performance modem transmit path, including symbol mapping, matched filtering, sample interpolation, and DAC interfacing. Using sophisticated DSP techniques, the High Data Rate Modulator IP Core can generate almost any modulation scheme up to 8 bits wide, such as (but not restricted to) BSPK, QPSK, offset- QPSK, 8/16/32/64/128/256QAM, 16/32APSK, and various “non-square” (NS) schemes, all to a high performance level and at high symbol rates. The High Data Rate Modulator IP Core is highly flexible, supporting continuously variable software-selectable symbol rates of between 2.5 kbaud and 40Mbaud, when operating with a fixed 100MHz system/DAC clock rate. This is the typical performance achievable when implementing the design using inexpensive FPGA devices, but increased data rates are possible by targeting the design to higher performance FPGA families which allow an increase in system clock rate. Once configured via the 32-bit microprocessor interface, the modulator operation is completely automatic .