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High bit rate Turbo Decoder core for 3GPP LTE/ LTE A
The 3GPP LTE Turbo Decoder IP Core V1.0 addresses the decoder implementation for the turbo coded transport channel compliant to 3GPP TS 36.212 V 10.5.0. The Turbo Decoder IP is a highly parallel and hardware efficient architecture to meet high throughputs demanded by the LTE and LTE Advanced standards and next generation large MIMO systems. The decoder exploits algebraic properties of the quadratic permutation polynomial (QPP) interleaver, to avoid memory contention issues when several MAP decoders are used in parallel.
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