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High Bandwidth Low Jitter De-Skew PLL

High bandwidth de-skew PLL for minimizing clock tree timing uncertainty. Low Power/ Low Area hard macro with industry leading jitter performance for its power/area class.

特色

Wide input and output frequency ranges
Duty cycle 48% -- 52%
Static Phase Offset 1% UI
Multiple synchronous output clocks
Small footprint (0.003mm2 to 0.04mm^2)
Low power
Low jitter:
Core supply voltage only
Built-in supply decoupling
Simple digital control interface

优势

4:1 VCO range allows any frequency below the maximum VCO rate to be de-skewed
High bandwidth PLL quickly adjusts to track input phase variations
No external components required
No additional supply decoupling required
Loop automatically adjusts for any input frequency, so no complicated programming is required