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High Bandwidth In-Order RISC-V CPU IP Core
特色
- 64-bit Core
- Ready for the most demanding workloads, Avispado supports large memory capacities with its 64-bit native data path.
- With its complete MMU support, Avispado is also Linux-ready, including multiprocessing.
- Vector Ready (optional VPU 823 - RISC-V vector unit)
- Avispado supports the upcoming RISC-V Vector Specification 1.0 as well as Semidynamics Open Vector Interface, giving you freedom of choice between your own custom vector unit and using Semidynamics offerings.
- Vector Instructions densely encode lots of computations, thereby reducing energy per operation.
- Vector Gather instructions support sparse tensor weights efficiently, helping machine learning workloads.
- Multiprocessor Ready
- Avispado supports cache-coherent Multiprocessing environments. Its native CHI interface can be tailored down to ACE or AXI, depending on your needs.
- Be it 2, 4, or hundreds of cores, Avispado is ready for your next SOC.
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RISC-V IP
- RISC-V ARC-V RMX-100 Ultra-low Power 32-bit Processor IP for Embedded Applications
- ARC-V RMX-500 power efficient 32-bit RISC-V processor for embedded applications
- ARC-V RHX-105 dual-issue, 32-bit RISC-V processor for real-time applications (multi-core)
- 32-bit Embedded RISC-V Functional Safety Processor
- 64-bit RISC-V Application Processor Core
- Dual-issue Linux-capable RISC-V core