90nm FTP Non Volatile Memory for Standard CMOS Logic Process
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HEVC/H.265 Decoder - Supports 1080p60, 4:2:2, 12Bits
VYUsync’s HEVC 1080p60, 4:2:2, 12-bit Decoder Core is a highly optimized video decompression engine targeted primarily at Xilinx FPGAs. It is a universal decoder and has been tested with more than 3000 industry standard test streams. The Decoder is compatible with any ASIC/FPGA/Software encoders in the market. The decoder has been proven on field and the customers are shipping the products with VYUsync HEVC Decoder IP.
It is well suited for various applications ranging from broadcast and professional video to high end consumer electronics. The decoder design is fully autonomous and does not require any external processor to aid the decode operation. The IO interface comprises of an input FIFO and an output frame buffer. Decoded data can also be provided on a serial bus with embedded sync information. The decoder requires DDR SDRAM to store reference pictures. The decoder solution is available either as a FPGA netlist or in source code format and can be customized to meet the requirements of end users.
It is well suited for various applications ranging from broadcast and professional video to high end consumer electronics. The decoder design is fully autonomous and does not require any external processor to aid the decode operation. The IO interface comprises of an input FIFO and an output frame buffer. Decoded data can also be provided on a serial bus with embedded sync information. The decoder requires DDR SDRAM to store reference pictures. The decoder solution is available either as a FPGA netlist or in source code format and can be customized to meet the requirements of end users.
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Block Diagram of the HEVC/H.265 Decoder - Supports 1080p60, 4:2:2, 12Bits
