RT-120 Compact Root of Trust for IoT and IIoT, sensors and gateways
HEVC/H.265 Decoder - Supports 1080p60, 4:2:2, 12Bits
It is well suited for various applications ranging from broadcast and professional video to high end consumer electronics. The decoder design is fully autonomous and does not require any external processor to aid the decode operation. The IO interface comprises of an input FIFO and an output frame buffer. Decoded data can also be provided on a serial bus with embedded sync information. The decoder requires DDR SDRAM to store reference pictures. The decoder solution is available either as a FPGA netlist or in source code format and can be customized to meet the requirements of end users.
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Block Diagram of the HEVC/H.265 Decoder - Supports 1080p60, 4:2:2, 12Bits

HEVC IP
- Enhanced Multi-Format Encoder Supporting AV1
- Up To 5 MPixel Multi-Format Encoder
- 1080p60 Multi-Format Decoder IP
- 4K/8K Scalable Multi-Format Video Decoding IP Core
- HEVC/H.265 + AVC/H.264 Codec IP Single-CORE for 4Kp60
- Multi-format decoder for 4K UHD with a single-core, 4:2:0 10-bit (max 8K). HEVC/H.265, AVC/H.264, VP9, AV1 and AVS2