VYUsync’s HEVC 4Kp60, 4:2:2, 10-bit Decoder Core is a highly optimized universal video decompression engine. The Decoder has been tested with more than 3000 industry standard test streams and is compatible with any ASIC/FPGA/Software encoders in the market. It is a sub frame latency decoder with lowest delay of 5 – 8 mili seconds for 4Kp60 Decode. The decoder has been proven on the field and trusted by leaders in the Broadcast Industry.
It is well suited for various applications ranging from broadcast and professional video to high end consumer electronics. The decoder design is fully autonomous and does not require any external processor to aid the decode operation. The IO interface comprises of an input FIFO and an output frame buffer. Decoded data can also be provided on a serial bus with embedded sync information. The decoder requires DDR SDRAM to store reference pictures. The decoder solution is available either as a FPGA netlist or in source code format and can be customized to meet the requirements of end users.