HEVC 4Kp60 Decoder, Supports 4:2:2, 10-bit decoding and 150Mbps bitrate
It is well suited for various applications ranging from broadcast and professional video to high end consumer electronics. The decoder design is fully autonomous and does not require any external processor to aid the decode operation. The IO interface comprises of an input FIFO and an output frame buffer. Decoded data can also be provided on a serial bus with embedded sync information. The decoder requires DDR SDRAM to store reference pictures. The decoder solution is available either as a FPGA netlist or in source code format and can be customized to meet the requirements of end users.
查看 HEVC 4Kp60 Decoder, Supports 4:2:2, 10-bit decoding and 150Mbps bitrate 详细介绍:
- 查看 HEVC 4Kp60 Decoder, Supports 4:2:2, 10-bit decoding and 150Mbps bitrate 完整数据手册
- 联系 HEVC 4Kp60 Decoder, Supports 4:2:2, 10-bit decoding and 150Mbps bitrate 供应商