MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, N7, N5A)
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HDMI 2.1 Tx- Rx PHY & Controller IP (Silicon Proven in TSMC 28HPC+)
The HDMI V2.1 Tx provides a complete single-link HDMI transmitter function complies with HDMI specification version 2.1. It consists of two modules, a physical layer and a link module. The PHY is upper compatible with DVI transmitter and implemented as a hard IP based on an TSMC 28nm HPC+ process, while the link module is implemented as a synthesizable soft IP. Built-in High-bandwidth Digital Content Protection (HDCP) cipher function protects the transmission of audio-visual contents.
The HDMI V2.1 Rx provides a complete single-link HDMI receiver function complies with HDMI specification version 2.1. It consists of two modules, a physical layer (PHY) and a link module. The PHY is upper compatible with DVI receiver and implemented as a hard IP based on an TSMC 28nm HPC+ process, while the link module is implemented as a synthesizable soft IP. Built-in High-bandwidth Digital Content Protection (HDCP) cipher function protects the transmission of audio-visual content.
The HDMI V2.1 Rx provides a complete single-link HDMI receiver function complies with HDMI specification version 2.1. It consists of two modules, a physical layer (PHY) and a link module. The PHY is upper compatible with DVI receiver and implemented as a hard IP based on an TSMC 28nm HPC+ process, while the link module is implemented as a synthesizable soft IP. Built-in High-bandwidth Digital Content Protection (HDCP) cipher function protects the transmission of audio-visual content.
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Block Diagram of the HDMI 2.1 Tx- Rx PHY & Controller IP (Silicon Proven in TSMC 28HPC+)
