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HDMI 2.1 Tx PHY in Samsung (14nm)
The Synopsys HDMI 2.1 TX Controller and PHY IP solutions,compliant with the High-Definition Multimedia Interface (HDMI) 2.1 specification, provide the necessary logic to implement and verify designs for various HDMI-based
applications. The IP provides quality digital video and audio transmission with up to 48Gbps aggregate bandwidth for uncompressed 8K resolution at 60Hz refresh rate. It supports key features of HDMI 2.1 including dynamic HDR and enhanced audio return channel (eARC), ensuring higher frame-by-frame video quality and most advanced audio formats. The IP also supports latest HDMI
2.1a addition for Source based tone mapping.
The complete power- and area-optimized HDMI 2.1 TX IP solution encompasses a suite of configurable digital controllers, high-speed,
mixed-signal PHY IP, verification IP, High-bandwidth Digital Camera Protection (HDCP) embedded security modules, Display Stream Compression (DSC) IP, all pre-integrated and shipped with a reference system. Having all necessary
design blocks for the HDMI subsystem, the IP solution enables system-on-chip (SoC) designers to lower integration risk and accelerate time-to-market.
applications. The IP provides quality digital video and audio transmission with up to 48Gbps aggregate bandwidth for uncompressed 8K resolution at 60Hz refresh rate. It supports key features of HDMI 2.1 including dynamic HDR and enhanced audio return channel (eARC), ensuring higher frame-by-frame video quality and most advanced audio formats. The IP also supports latest HDMI
2.1a addition for Source based tone mapping.
The complete power- and area-optimized HDMI 2.1 TX IP solution encompasses a suite of configurable digital controllers, high-speed,
mixed-signal PHY IP, verification IP, High-bandwidth Digital Camera Protection (HDCP) embedded security modules, Display Stream Compression (DSC) IP, all pre-integrated and shipped with a reference system. Having all necessary
design blocks for the HDMI subsystem, the IP solution enables system-on-chip (SoC) designers to lower integration risk and accelerate time-to-market.
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