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HDMI 2.1 IP Core
The Bitec HDMI 2.1b IP Core enables HDMI interconnectivity in FPGA or ASIC devices. Supporting uncompressed video formats to 8K60 4:2:0 and beyond for DSC Compressed formats. The IP is rich in parameterization to enable optimized designs for both FPGA and ASIC flows.
Used in over 600 million devices, HDMI represents the most common interconnect standard for high definition video and audio.
The Bitec HDMI 2.1 IP Core enables HDMI inter-connectivity in FPGA or ASIC devices. Supporting uncompressed video formats to 8K60 4:2:0 and beyond, the Core is rich in parameterization to accomodatethe challenging timing closure requirements of FPGA to the power/size requirements of ASIC. The core also provides support for ARC/eARC and CEC 2.0.
Both Video and Audio is supported with added low-level access to Auxiliary data packets. This feature allows low level development and testing of HDMI interfaces. It also allows a more flexible interface to the latest 3D and 8K video formats and control packets.
The core provides convenient interfacing to 3rd party SERDES for rapid development of image processing systems. It is also designed to operate in parallel with the Bitec DP 1.4 IP Core to achieve DP++ compatibility.
Used in over 600 million devices, HDMI represents the most common interconnect standard for high definition video and audio.
The Bitec HDMI 2.1 IP Core enables HDMI inter-connectivity in FPGA or ASIC devices. Supporting uncompressed video formats to 8K60 4:2:0 and beyond, the Core is rich in parameterization to accomodatethe challenging timing closure requirements of FPGA to the power/size requirements of ASIC. The core also provides support for ARC/eARC and CEC 2.0.
Both Video and Audio is supported with added low-level access to Auxiliary data packets. This feature allows low level development and testing of HDMI interfaces. It also allows a more flexible interface to the latest 3D and 8K video formats and control packets.
The core provides convenient interfacing to 3rd party SERDES for rapid development of image processing systems. It is also designed to operate in parallel with the Bitec DP 1.4 IP Core to achieve DP++ compatibility.
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