You are here:
HDMI 2.1 Audio PLL in Samsung (14nm)
The Synopsys DesignWare HDMI 2.1 RX Controller and PHY IP solutions, compliant with the High-Definition Multimedia Interface (HDMI) 2.1 specification, provide the necessary logic to implement and verify designs for various HDMI-based applications. The silicon-proven HDMI 2.1 IP provides quality digital video and audio transmission with up to 48Gbps aggregate bandwidth for uncompressed 8K resolution at 60Hz refresh rate. It supports the required features of HDMI 2.1 including dynamic HDR and enhanced audio return channel (eARC) and more, ensuring higher video quality and most advanced audio formats.
The complete power- and area-optimized HDMI 2.1 RX IP solution encompasses a suite of configurable digital controllers, high-speed, mixedsignal PHYs, PLL, verification IP, High-Bandwidth Digital Content Protection (HDCP) IP, IP Prototyping Kits, Linux software drivers, and IP subsystems. Having all necessary design blocks for the HDMI subsystem enables systemon-chip (SoC) designers to lower integration risk and accelerate time-to-market.
The complete power- and area-optimized HDMI 2.1 RX IP solution encompasses a suite of configurable digital controllers, high-speed, mixedsignal PHYs, PLL, verification IP, High-Bandwidth Digital Content Protection (HDCP) IP, IP Prototyping Kits, Linux software drivers, and IP subsystems. Having all necessary design blocks for the HDMI subsystem enables systemon-chip (SoC) designers to lower integration risk and accelerate time-to-market.
查看 HDMI 2.1 Audio PLL in Samsung (14nm) 详细介绍：
- 查看 HDMI 2.1 Audio PLL in Samsung (14nm) 完整数据手册
- 联系 HDMI 2.1 Audio PLL in Samsung (14nm) 供应商