Single Port, Ultra Low Leakage, GF 22FDX, Single Port Compiler
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HDMI 2.0 Rx PHY & Controller IP (Silicon Proven in TSMC 28HPC+)
This HDMI 2.O Rx IP provides a complete HDMI receiver function and complies with HDMI specification version 2.0b. It consists of two modules, a physical layer (PHY) and a link module. The PHY is upper compatible with DVI receiver and implemented as a hard IP based on TSMC 28HPC+ CMOS logic process, while the link module is implemented as a synthesizable soft IP. Built-in High-bandwidth Digital Content Protection (HDCP) cipher protects the transmission of audiovisual content
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Block Diagram of the HDMI 2.0 Rx PHY & Controller IP (Silicon Proven in TSMC 28HPC+)
